As semiconductor devices have been in a trend toward high integration and high density in recent years, circuit interconnects are also becoming smaller and finer, and the larger number of layers are used to form multilayer interconnects. The multilayer interconnects with the finer circuits entail greater surface steps which reflect surface irregularities of lower layers. An increase in the number of interconnect layers would result in poor film formation (or step coverage) over stepped configurations of thin films. Therefore, better multilayer interconnects need to have the improved step coverage and proper surface planarization. Furthermore, miniaturization of a photolithographic process necessitates a smaller depth of focus in a photolithographic optical system, and therefore a surface of the semiconductor device needs to be planarized such that the irregularities or steps on the surface of the semiconductor device will fall within the depth of focus.
Thus, in a process of manufacturing semiconductor devices, it becomes increasingly important to planarize a surface of the semiconductor device. One of the most important techniques in the surface planarization is chemical mechanical polishing (CMP). This chemical mechanical polishing is performed by bringing a wafer into sliding contact with a polishing surface of a polishing pad, while supplying a polishing liquid, containing abrasive particles such as silica (SiO2) therein, onto the polishing surface to thereby polish the wafer.
A CMP apparatus is a polishing apparatus for chemically and mechanically polishing a wafer. Such a polishing apparatus, which is called CMP apparatus, includes a plurality of polishing tables and a plurality of polishing heads in order to perform multistage polishing of a wafer. A wafer is transported to polishing pads on polishing tables successively, and is polished on the polishing pads by polishing heads successively. For example, rough polishing of a wafer is performed as a first-stage polishing, and final polishing of the wafer is performed as a second-stage polishing.
The polishing apparatus is required to execute polishing recipes adapted to various polishing processes. To meet such requirement, high-performance polishing heads are used as the above-described plurality of polishing heads. More specifically, the polishing heads may each include a membrane for pressing a plurality of areas of a wafer independently, a retainer ring for pressing a polishing pad in an area around the wafer, etc.
However, such a high-performance polishing head has a complicated structure and has costly consumables (the membrane, the retainer ring, etc.), and therefore entails an increased maintenance cost and an increased running cost. Further, a frequency of maintenance work will also increase, resulting in a decrease in an operation rate of the apparatus.
The above polishing head has a plurality of pressure chambers formed by the membrane. The pressure chambers are capable of changing the internal pressures, so that the polishing head can apply different polishing pressures to a plurality of areas of a wafer. Therefore, the polishing head can polish the wafer while individually controlling polishing rates in the respective areas of the wafer.
However, the polishing head of this type cannot control the polishing rate in smaller areas than the pressure chambers. It is possible to perform finer control of a wafer profile by using more pressure chambers, but there is a limit on the number of pressure chambers that can be provided in the polishing head. Furthermore, the above-described polishing head is not able to positively control a polishing rate of a wafer at a boundary between the pressure chambers, and therefore the polishing rate may be low at the boundary between the pressure chambers.
With the progress toward higher integration of semiconductor devices and in order to increase the productivity in manufacturing of semiconductor devices, there has recently been a strong demand for higher-performance polishing apparatus. Performance characteristics as required for the polishing apparatus may include a planarization capability (a capability of Dishing/Erosion), a polishing rate (also called a removal rate), a uniformity of polishing-rate distribution over a wafer surface, a low defect level of polished wafer, a throughput of the polishing apparatus, etc.
The above-described performance characteristics often require contradictory polishing conditions. For example, polishing with a low pressure is typically desirable for enhancing the planarization capability, while polishing with a high pressure is desirable for increasing the polishing rate and the throughput. In addition, polishing using a high-hardness polishing pad is typically desirable for enhancing the planarization capability, while use of a low-hardness polishing pad is often desirable in order to achieve a low defect level of a polished wafer.
Japanese laid-open patent publication No. 2010-50436 discloses a polishing apparatus having multiple polishing heads. When such a polishing apparatus is used to perform multistage polishing, different polishing liquids and different polishing pads are used in accordance with types of intended polishing, such as rough polishing, final polishing, etc., thus resulting in basically different polishing-rate distributions. Therefore, polishing head control characteristics, which are necessary to improve the uniformity of polishing rate in a wafer surface, differ between rough polishing and final polishing.